First Session
Scaling NVDIMM-N architecture for System Acceleration in DDR5 and CXL-Enabled Applications
Date:
Arthur Sainio, SMART DRAM Product Director and Pekon Gupta, Solutions Architect
In this session, attendees will learn
- NVDIMM-N architecture transition from DDR4 to DDR5 without significant changes.
- Any latency-sensitive data that is continuously changing can benefit from NVDIMM and NV-XMM.
- DDR5 NVDMM-N is near-term and will fill a gap for high performance, low latency persistent memory applications
- And More
Second Session
Computational Memory: Moving compute near Data with Kestral (Enabling Processing in Memory (PIM) with Kestral)
Date:
Arthur Sainio, SMART DRAM Product Director and Pekon Gupta, Solutions Architect
In this session, attendees will learn
- How offloading of static functions to memory device not only reduces the wasteful copy and discard approach, but also improves efficiency and frees the bus for other performance critical workloads.
- How attaching large pool of memory to PCIe Gen 4.0 serial bus gives dual advantages of enabling expansion and freeing critical DDR slots for high bandwidth interfaces like DDR5 DIMMs.
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